1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and more particularly to a method of fabricating a semiconductor device by forming resist masks by using both photo-lithography and electron beam lithography and by using them as patterning masks of underlying layers.
2. Description of the Related Art
Hitherto, steps of forming a conductive film on the whole surface of a semiconductor substrate and of patterning and processing it into a predetermined shape to form a wiring layer and the like are implemented in fabricating semiconductor devices.
Among the steps of forming the wiring layer, steps of forming a gate electrode wire and a wire connecting region of a MOS transistor will be explained below as conventional technology with reference to FIGS. 1 through 3. It is noted that in the following explanation, the wire connecting region is assumed to be connected with the gate electrode wire. Further, it is assumed that this wire connecting region is formed to be properly positioned and so that its size is larger than the gate electrode wire in order to contact a wiring layer which is not shown in the figures.
FIG. 4 (c) which is discussed below with respect to a description of the embodiments of the present invention, each of FIGS. 1(a), 2(a) and 3(a) is a sectional view of a part corresponding to a section along a line A--A in FIG. 4(c) and each of FIGs. 1(b), 2(b) and 3(b) is a sectional view of a part corresponding to a section along a line B--B in FIG. 4(c).
First, a field insulating film 112 is formed on an element separating region of a semiconductor substrate 111 and a gate insulating film 113 is formed on an element region of the semiconductor substrate 111 as shown in FIGs. 1(a) and 1(b). While a case in which the field insulating film 112 is formed by means of LOCOS (Local Oxidation of Silicon) is shown in the figures, it may also be formed by means of STI (Shallow Trench Isolation). Next, a conductive film 114 is formed on these insulating films 112 and 113 as a polycrystal silicon film or the like to form the gate electrode wire. Then, a cap insulating film 115 is formed on the conductive film 114. It is noted that the conductive film 114 and the cap insulating film 115 are deposited by means of CVD (Chemical Vapour Deposition) or sputtering. After that, a resist for photo-lithography or for electron beam lithography is applied on the cap insulating film 115 and a resist pattern 116 is formed by exposing the resist into the shape of the gate electrode wire by means of photo-lithography or electron beam lithography and by developing the exposed resist.
Following that, the cap insulating film 115 is patterned by means of anisotropic etching by using the resist pattern 116 as a mask as shown in FIGS. 2(a) and 2(b). Next, the resist pattern 116 used as the mask in etching is removed by means of ashing or the like.
Then, the conductive film 114 is patterned by means of anisotropic etching by using the patterned cap insulating film 115 as a mask to form the gate electrode wire and the wiring connecting section connected thereto as shown in FIGS. 3(a) and 3(b).
While the example described above shows the method for forming the gate electrode wire and the wire connecting region connected thereto of the MOS transistor, the same fabricating steps may also be used in forming a wiring layer and a wire connecting region between other elements.
While photo-lithography in which g-ray, i-ray or KrF excimer laser is used as a light source is generally used in patterning the resist used as a mask for forming a wire in the prior art, it is also possible to use electron beam lithography by which a pattern is drawn by means of electron beams.
Photo-lithography is a method normally used in forming a resist pattern and is suited for mass-production of semiconductor devices because its throughput is relatively high. However, it has a problem in terms of resolution in view of the fabrication of ultra LSIs which will be refined further in the future. According to the present photo-lithography technology, a width of about 0.25 .mu.m is considered to be the limit in patterning even if a KrF excimer laser is used as a light source. While the design rule for wiring is predicted to become around 0.1 .mu.m or less following the trend of the refinement of ultra LSIs of the future, it is difficult to pattern a wire to meet such a design rule by using the present photo-lithography technology.
Meanwhile, electron beam lithography has a higher resolution as compared to photo-lithography and is considered to be fully able to enable patterning to meet the design rule of around 0.1 .mu.m or less. However, as compared to photo-lithography, it has had a problem that its throughput is extremely low. This is because, while a plane of a resist can be exposed in a wide range at one time by photo-lithography, the plane of the resist cannot be exposed in a wide range at one time by electron beam lithography and it is necessary to trace a pattern on a region to be exposed with the electron beam.
Normally, a pattern whose design rule is relatively large, i.e., a pattern which can be fully patterned even by using the present photo-lithography techniques, and a pattern whose design rule is relatively small, i.e., a pattern which is difficult to pattern by the present photo-lithography techniques, are mixed in patterns of wires among elements of a semiconductor integrated circuit. In such cases, typically, an area of the pattern whose design rule is relatively large, is larger than an area of a pattern whose rule is relatively small. It is then conceivable to use electron beam lithography only in forming the pattern whose design rule is small and which is hard to pattern by photo-lithography and to use photo-lithography in forming patterns other than that in order to improve both the throughput and the resolution.
However, types of resists formed as a mask for etching by photo-lithography and electron beam lithography are different. Accordingly, it is impossible to simply use both photo-lithography and electron beam lithography. If both photo-lithography and electron beam lithography are to be used by using resists which correspond to respective lithographs, it may be necessary to perform electron beam lithography after forming a mask for covering a resist pattern formed by photo-lithography so that it is not affected by electron beams or to remove the mask after using it as a mask for electron beam lithography, for example, thus increasing the number of processing steps. Meanwhile, although a resist which may be exposed by both light and electron beams without reducing resolution is under development, it is not yet available for practical use.
Further, although it is conceivable to pattern all of the patterns having large and small design rules by electron beam lithography, the throughput drops significantly in this case. This is because, while a plane of a resist can be exposed in a wide range at one time by photo-lithography, this is not the case for electron beam lithography. Instead, it is necessary to trace a pattern on a region to be exposed with the electron beam, as described above. Presently, while a time necessary for exposing resists by photo-lithography per wafer is about several minutes including a time necessary for moving the wafer, it takes several hours per wafer by electron beam lithography. Accordingly, it is not realistic to expose resist patterns only by electron beam lithography in fabricating semiconductor devices which are mass-produced specially in a large scale production.